Key Takeaways
- Researchers at Fraunhofer IPMS propose three methods to improve planarization in STI CMP processes.
- Methods lead to significant reductions in within-die non-uniformity and oxide dishing in advanced nodes.
- These techniques could facilitate the use of silica slurry in applications where cost and supply concerns are critical.
Research Overview
A recent paper entitled “Reduced Topography After Stop on Nitride (SON) STI CMP Through Improved Post-Bulk Planarity for Diverse Layouts in Advanced Nodes” was released by researchers at Fraunhofer IPMS. The study investigates three effective methods for enhancing planarization during a ceria-free, two-step STI CMP process, specifically focusing on patterns representative of 2X nm technology.
The research reveals that within-die non-uniformity after bulk CMP can be significantly reduced through three main strategies:
- Higher Oxide Overburden: Increasing the oxide thickness provides better material to work with during the polishing process.
- Reduced Bulk Polish Pressure: Lowering the pressure during bulk polishing enhances uniformity by minimizing localized wear.
- Intermittent Polishing: This innovative approach combines polishing and water rinse intervals with ongoing conditioning. The study found that these methods can reduce within-die non-uniformity (WIDNU) by up to 15%, 30%, and 41%, respectively.
When these techniques are used in conjunction, the results are impressive, achieving up to a 33% decrease in WIDNU post-SON. Furthermore, oxide dishing—especially in larger areas measuring 0.1 and 1 mm—is reduced by as much as 43% and 46%, respectively.
Importantly, the implementation of these methods requires only minimal process modifications. This opens the door for replacing common ceria slurry with silica slurry in certain applications, particularly where cost, particle contamination, sustainability, and supply risks are of paramount importance.
The research highlights a significant step toward advancing semiconductor manufacturing processes by providing viable solutions to common challenges in STI CMP. By adopting these strategies, manufacturers can potentially enhance the efficiency and cost-effectiveness of their operations.
For further details, the technical paper is published in the IEEE Transactions on Semiconductor Manufacturing and can be accessed via doi: 10.1109/TSM.2025.3584390.
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